Transistor substrate and display device manufactured from the transistor substrate

ABSTRACT

A transistor substrate is provided. The transistor substrate includes a plurality of data lines and a plurality of scan lines, wherein the scan lines intersects with the data lines to define a plurality of pixel units. One of the pixel units includes a first electrode having a slit substantially parallel to the data lines. The pixel units include a second electrode and a switching transistor. The switching transistor includes a gate electrode connecting to one of the scan lines. The gate electrode has a first edge substantially parallel to the extending direction of the scan lines. The switching transistor includes a drain electrode electrically connected to one of the first electrode and the second electrode. The drain electrode includes an extending portion which extends toward the slit and extends away from an extending line of the first edge. The drain electrode and the slit have an overlapping region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No.105113233, filed on Apr. 28, 2016, the entirety of which is incorporatedby reference herein.

BACKGROUND Technical Field

The disclosure relates to a transistor substrate and a display devicemanufactured from the transistor substrate. The disclosure in particularrelates to a transistor substrate including an electrode having a slitand a display device manufactured from the transistor substrate.

Description of the Related Art

Display devices have been widely used in the display components of avariety of products. Liquid-crystal displays (LCDs) utilize theproperties of liquid-crystal molecules, which have differentpolarization or reflection effects to lights under different arrangementstates, so as to control the amounts of the transmitting lights. Theseliquid-crystal displays thus create images. The traditional twistednematic (TN) liquid-crystal displays have outstanding transmissionproperties, but the visual angles thereof are quite narrow due to thestructural and optical features of the liquid-crystal molecules.

To solve this problem, manufacturers have recently developed variouswide-view liquid-crystal display devices, such as fringe-field switching(FFS) liquid-crystal displays, in-plane switching (IPS) liquid-crystaldisplays, and so on.

However, existing display devices have not been satisfactory in everyrespect. Therefore, a display device which may further improve theaperture ratio or the contrast ratio is needed.

SUMMARY

The present disclosure provides a transistor substrate, including aplurality of data lines and a plurality of scan lines intersecting withthe plurality of data lines to define a plurality of pixel units. One ofthe pixel units includes a first electrode, a second electrode, and aswitching transistor. The first electrode has a slit that issubstantially parallel to the data lines. One of the first electrode andthe second electrode is used for receiving a pixel voltage signal, andthe other of the first electrode and the second electrode is used forreceiving a common voltage signal. The switching transistor includes agate electrode and a drain electrode. The gate electrode is connected toone of the scan lines and includes a first edge that is substantiallyparallel to the extending direction of the scan lines. The drainelectrode is electrically connected to either the first electrode or thesecond electrode. The drain electrode includes an extending portion,wherein the extending portion extends toward the slit and extends awayfrom an extending line of the first edge. The drain electrode and theslit have an overlapping region.

The present disclosure also provides a display device, including: atransistor substrate as described above; an opposing substrate disposedopposite to the transistor substrate; and a display medium disposedbetween the transistor substrate and the opposing substrate.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 is a top view of the transistor substrate of the display devicein accordance with some embodiments of the present disclosure;

FIG. 2A is a partially enlarged figure of the transistor substrate ofthe display device in FIG. 1;

FIG. 2B is a cross-sectional view along line 2B-2B in FIG. 2A inaccordance with some embodiments of the present disclosure;

FIG. 2C is a top view of the transistor substrate of the display devicein accordance with some embodiments of the present disclosure;

FIG. 3A is a diagram showing the relationship between the length and theaperture ratio of the extending portion of the drain electrode withinthe overlapping region in accordance with some embodiments of thepresent disclosure;

FIG. 3B is a diagram showing the relationship between the length and thelight transmittance of the extending portion of the drain electrodewithin the overlapping region in accordance with some embodiments of thepresent disclosure;

FIG. 3C is a diagram showing the relationship between the length and thecontrast ratio of the extending portion of the drain electrode withinthe overlapping region in accordance with some embodiments of thepresent disclosure;

FIG. 4 is a cross-sectional view of the transistor substrate of thedisplay device in accordance with another embodiment of the presentdisclosure; and

FIG. 5 is a top view of the transistor substrate of the display devicein accordance with another embodiment of the present disclosure.

DETAILED DESCRIPTION

The transistor substrate of the present disclosure and the displaydevice manufactured from the transistor substrate are described indetail in the following description. In the following detaileddescription, for purposes of explanation, numerous specific details andembodiments are set forth in order to provide a thorough understandingof the present disclosure. The specific elements and configurationsdescribed in the following detailed description are set forth in orderto clearly describe the present disclosure. It will be apparent,however, that the exemplary embodiments set forth herein are used merelyfor the purpose of illustration, and the inventive concept may beembodied in various forms without being limited to those exemplaryembodiments. In addition, the drawings of different embodiments may uselike and/or corresponding numerals to denote like and/or correspondingelements in order to clearly describe the present disclosure. However,the use of like and/or corresponding numerals in the drawings ofdifferent embodiments does not suggest any correlation between differentembodiments. In addition, in this specification, expressions such as“first material layer disposed on/over a second material layer”, mayindicate the direct contact of the first material layer and the secondmaterial layer, or it may indicate a non-contact state with one or moreintermediate layers between the first material layer and the secondmaterial layer. In the above situation, the first material layer may notbe in direct contact with the second material layer.

It should be noted that the elements or devices in the drawings of thepresent disclosure may be present in any form or configuration known tothose with ordinary skill in the art. In addition, the expressions “alayer overlying another layer”, “a layer is disposed above anotherlayer”, “a layer is disposed on another layer” and “a layer is disposedover another layer” may indicate that the layer is in direct contactwith the other layer, or that the layer is not in direct contact withthe other layer, there being one or more intermediate layers disposedbetween the layer and the other layer.

In addition, in this specification, relative expressions are used. Forexample, “lower”, “bottom”, “higher” or “top” are used to describe theposition of one element relative to another. It should be appreciatedthat if a device is flipped upside down, an element that is “lower” willbecome an element that is “higher”.

The terms “about” and “substantially” typically mean +/−20% of thestated value, more typically +/−10% of the stated value, more typically+/−5% of the stated value, more typically +/−3% of the stated value,more typically +/−2% of the stated value, more typically +/−1% of thestated value and even more typically +/−0.5% of the stated value. Thestated value of the present disclosure is an approximate value. Whenthere is no specific description, the stated value includes the meaningof “about” or “substantially”.

It should be understood that, although the terms first, second, thirdetc. may be used herein to describe various elements, components,regions, layers, portions and/or sections, these elements, components,regions, layers, portions and/or sections should not be limited by theseterms. These terms are only used to distinguish one element, component,region, layer, portion or section from another region, layer or section.Thus, a first element, component, region, layer, portion or sectiondiscussed below could be termed a second element, component, region,layer, portion or section without departing from the teachings of thepresent disclosure.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this disclosure belongs. It should be appreciated that,in each case, the term, which is defined in a commonly used dictionary,should be interpreted as having a meaning that conforms to the relativeskills of the present disclosure and the background or the context ofthe present disclosure, and should not be interpreted in an idealized oroverly formal manner unless so defined.

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. The drawings are not drawn toscale. In addition, structures and devices are shown schematically inorder to simplify the drawing.

In the description, relative terms such as “lower,” “upper,”“horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and“bottom” as well as derivative thereof (e.g., “horizontally,”“downwardly,” “upwardly,” etc.) should be construed to refer to theorientation as then described or as shown in the drawing underdiscussion. These relative terms are for convenience of description anddo not require that the apparatus be constructed or operated in aparticular orientation. Terms concerning attachments, coupling and thelike, such as “connected” and “interconnected,” refer to a relationshipwherein structures are secured or attached to one another eitherdirectly or indirectly through intervening structures, as well as bothmovable or rigid attachments or relationships, unless expresslydescribed otherwise.

The term “substrate” is meant to include devices formed within atransparent substrate and the layers overlying the transparentsubstrate. All transistor element needed may already be formed over thesubstrate. However, the substrate is represented with a flat surface inorder to simplify the drawing. The term “substrate surface” is meant toinclude the uppermost exposed layers on a transparent substrate, such asan insulating layer and/or metallurgy lines.

In accordance with the embodiments of the present disclosure, the drainelectrode overlaps with the end portion of the slit of the pixelelectrode or the common electrode so as to shield light leaks of the endportion, which in turn improves the aperture ratio or the contrast rateof the display device.

FIG. 1 is a top view of a transistor substrate 102 of a display device100 in accordance with some embodiments of the present disclosure. FIG.2A is a partially enlarged figure of one of the pixel units of thetransistor substrate 102 of the display device 100 in FIG. 1. As shownin FIGS. 1 and 2A, the transistor substrate 102 may include a pluralityof scan lines (gate lines) 104 extending along a first direction A1 anda plurality of data lines 106 intersecting the scan lines 104. The scanlines 104 extend along direction A1, and data lines 106 aresubstantially perpendicular or orthogonal to the scan-lines and extendalong a second direction A2.

In addition, the plurality of scan lines 104 and the plurality of datalines 106 intersect each other to define a plurality of pixel units 108,such as sub-pixels. One of the pixel units 108 includes a switchingtransistor 110.

The data lines 106 may provide a signal to the pixel units 108 throughthe switching transistor 110. The scan lines (gate lines) 104 mayprovide the scanning pulse signal to the pixel units 108 through theswitching transistor 110 and control the pixel units 108 in coordinationwith the aforementioned signal.

The switching transistor 110 includes a semiconductor layer 152, asource electrode 112, a drain electrode 114 and a gate electrode 116.The gate electrode 116 is connected to one of the scan lines 104 andextends from the scan line 104 along the second direction A2. The sourceelectrode 112 is a portion of the data line 106.

FIG. 2B is a cross-sectional view along line 2B-2B in FIG. 2A inaccordance with some embodiments of the present disclosure. As shown inFIG. 2B, the transistor substrate 102 may include a substrate 118. Thesubstrate 118 may include, but is not limited to, a transparentsubstrate, such as a glass substrate, a ceramic substrate, a plasticsubstrate, or any other suitable transparent substrate. Theabove-mentioned data lines 106, the source electrode 112 and the drainelectrode 114 are disposed on the substrate 118. In addition, theinsulating layer 120 is disposed between the data lines 106 and thesubstrate 118, between the source electrode 112 and the substrate 118,and between the drain electrode 114 and the substrate 118. Theinsulating layer 120 is illustrated as one layer for simplicity. Inpractical processes, the insulating layer 120 may include more than asingle layer. For example, the insulating layer 120 may include a gatedielectric layer and a buffer layer.

The materials of the gate electrode 116 and gate line 104 may includeone or more types of metal, metal nitride, conductive metal oxide, or acombination thereof. The metal may include, but is not limited to,molybdenum, tungsten, titanium, tantalum, platinum, or hafnium. Themetal nitride may include, but is not limited to, molybdenum nitride,tungsten nitride, titanium nitride or tantalum nitride. The conductivemetal oxide may include, but is not limited to, ruthenium oxide orindium tin oxide. The gate electrode 116 and gate line 104 may be formedby the chemical vapor deposition (CVD), sputtering, resistive thermalevaporation, electron beam evaporation, or any other suitable methods.

The material of the gate dielectric layer 120 may include silicon oxide,silicon nitride, silicon oxynitride, high-k dielectric material, anyother suitable dielectric material, or a combination thereof. The high-kdielectric material may include, but is not limited to, metal oxide,metal nitride, metal silicide, transition metal oxide, transition metalnitride, transition metal silicide, metal oxynitride, metal aluminate,zirconium silicate, zirconium aluminate. For example, the material ofthe high-k dielectric material may include, but is not limited to, LaO,AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃(STO), BaTiO₃(BTO), BaZrO, HfO₂, HfO₃,HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfSiO, HfTaTiO,HfAlON, (Ba,Sr)TiO₃(BST), Al₂O₃, any other suitable high-k dielectricmaterial, or a combination thereof. The gate dielectric layer 120 may beformed by chemical vapor deposition or spin-on coating. The chemicalvapor deposition may include, but is not limited to, low pressurechemical vapor deposition (LPCVD), low temperature chemical vapordeposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD),plasma enhanced chemical vapor deposition (PECVD), atomic layerdeposition (ALD), or any other suitable method.

Still referring to FIG. 2B, the data line 106 (including the sourceelectrode 112) and the drain electrode 114 are disposed on theinsulating layer 120. The materials of the data line 106 (including thesource electrode 112) and the drain electrode 114 may include, but isnot limited to, copper, aluminum, molybdenum, tungsten, gold, cobalt,nickel, platinum, titanium, iridium, rhodium, an alloy thereof, acombination thereof, or any other conductive material. In otherembodiments, the data line 106 (including the source electrode 112) andthe drain electrode 114 may include a nonmetal material as long as thematerial is conductive. The material of the data line 106 (including thesource electrode 112) and the drain electrode 114 may be formed bychemical vapor deposition (CVD), sputtering, resistive thermalevaporation, electron beam evaporation, or any other suitable method. Insome embodiments, the materials of the data line 106 (including thesource electrode 112) and the drain electrode 114 may be the same, andthe data line 106 (including the source electrode 112) and the drainelectrode 114 may be formed in the same deposition step. However, inother embodiments, the data line 106 (including the source electrode112) and the drain electrode 114 may be formed in different depositionsteps, and the materials of the data line 106 (including the sourceelectrode 112) and the drain electrode 114 may be different from eachother.

Still referring to FIG. 2B, the transistor substrate 102 may furtherinclude a first insulating layer 122, which covers the data lines 106(including the source electrode 112), the drain electrode 114 and thegate dielectric layer 120. The material of the first insulating layer122 may include an organic material or an inorganic material such assilicon nitride, silicon oxide, or silicon oxynitride. The firstinsulating layer 122 may be formed by chemical vapor deposition (CVD) orspin-on coating. The chemical vapor deposition may include, but is notlimited to, low pressure chemical vapor deposition (LPCVD), lowtemperature chemical vapor deposition (LTCVD), rapid thermal chemicalvapor deposition (RTCVD), plasma enhanced chemical vapor deposition(PECVD), atomic layer deposition (ALD), or any other suitable method.

Moreover, in other embodiments, the material of the first insulatinglayer 122 may include the combinations of the organic insulatingmaterials or the inorganic insulating materials.

Still referring to FIG. 2B, the transistor substrate 102 may furtherinclude a common electrode 124 disposed on the first insulating layer122. The common electrode 124 is used for receiving a common voltagesignal.

Still referring to FIG. 2B, the transistor substrate 102 may furtherinclude a second insulating layer 126 covering the common electrode 124.The second insulating layer 126 may include, but is not limited to,silicon nitride, silicon oxide, or silicon oxynitride.

Still referring to FIG. 2B, the transistor substrate 102 may furtherinclude a pixel electrode 128 disposed on the second insulating layer126. The pixel electrode 128 is used for receiving a pixel voltagesignal. The common electrode 124 can be disposed corresponding to thepixel electrode 128. In addition, the pixel electrode 128 iselectrically connected to the drain electrode 114 of the switchingtransistor 110 through an opening 130 as shown in FIG. 2A. Thus, thepixel electrode 128 can receive the pixel voltage signal via the drainelectrode 114. The drain electrode 114 can be electrically connected toone of the plurality of data lines 106.

Moreover, still referring to FIG. 2B, the display device 100 may furtherinclude an opposing substrate 132 disposed opposite to the transistorsubstrate 102, and a display medium 134 disposed between the transistorsubstrate 102 and the opposing substrate 132.

The display device 100 may be, but is not limited to, a touchliquid-crystal display such as a thin film transistor liquid-crystaldisplay. The liquid-crystal display may include, but is not limited to,a twisted nematic (TN) liquid-crystal display, a super twisted nematic(STN) liquid-crystal display, a double layer super twisted nematic(DSTN) liquid-crystal display, a vertical alignment (VA) liquid-crystaldisplay, an in-plane switching (IPS) liquid-crystal display, acholesteric liquid-crystal display, a blue phase liquid-crystal display,a fringe-field switching (FFS) liquid-crystal display, or any othersuitable liquid-crystal display.

In some embodiments, the opposing substrate 132 serves as a color filtersubstrate. In particular, the opposing substrate 132, which serves as acolor filter substrate, may include a substrate 136, a light-shieldinglayer 138 disposed over the substrate 136, a color filter layer 140disposed over the light-shielding layer 138 and the substrate 136, and aovercoat layer 142 covering the light-shielding layer 138 and the colorfilter layer 140.

The substrate 136 may be a transparent substrate such as a glasssubstrate, a ceramic substrate, a plastic substrate, or any othersuitable transparent substrate. The light-shielding layer 138 may be,but is not limited to, black photoresist, black printing ink, or blackresin. The color filter layer 140 may include a red color filter layer,a green color filter layer, a blue color filter layer, or any othersuitable color filter layer.

FIG. 2C is a top view of the transistor substrate 102 of the displaydevice 100 in accordance with some embodiments of the presentdisclosure, which shows the same transistor substrate 102 and the samelight-shielding layer 138 of the opposing substrate as in FIG. 1. Insome embodiments, as shown in FIG. 2C, the light-shielding layer 138defines a pixel aperture region 144. In other words, the region of thetransistor substrate 102 that is not shielded by the light-shieldinglayer 138 is the pixel aperture region 144, and the region of thetransistor substrate 102 that corresponds to the light-shielding layer138 of the opposing substrate 132 is the light-shielding region.

Referring to FIG. 2A, showing two adjacent scan lines 104 and twoadjacent data lines 106 to define a pixel unit 128, the pixel electrode128 has a slit 146, and the slit 146 is substantially parallel to thedata line 106. In addition, the gate electrode 116 includes a first edge116E. The first edge 116E is substantially parallel to the extendingdirection A1 of the scan line 104, and is the edge of the gate electrode116 which is farthest from the corresponding scan line 104. The firstedge 116E is adjacent to the slit 146. Moreover, the drain electrode 114includes an extending portion 114A. The extending portion 114A extendstoward the slit 146 and extends away from an extending line 116EA of thefirst edge 116E. The drain electrode 114 and the slit 146 have anoverlapping region. In some embodiments, the extending portion 114A ofthe drain electrode 114 at least partially overlaps the slit 146 of thepixel electrode 128.

In particular, the slit 146 includes a major axis portion 146A and acurved portion 146B (or is referred to as an end portion 146B) connectedto the major axis portion 146A. Using the extending direction A1 of thescan line 104 as a basis, the slope of the edge of the major axisportion 146A is different from the slope of the edge of the curvedportion 146B. For example, in accordance with some embodiments of thepresent disclosure, the edge of the major axis portion 146A issubstantially parallel to the data line 106, and the edge of the curvedportion 146B is substantially not parallel to the data line 106.

Furthermore, in accordance with some embodiments of the presentdisclosure, the point of the edge of the slit 146 where the slopethereof starts to be different from the slope of the edge of the dataline 106 is point 146P. The line crossing through point 146P andparallel to the extending direction A1 of the scan line 104 is line146PL. Line 146PL is the boundary between the major axis portion 146Aand the curved portion 146B. The overlapping region between theextending portion 114A of the drain electrode 114 and the slit 146 islocated within the curved portion 146B.

In the display device 100, light leaks may occur in the regioncorresponding to the curved portion 146B of the slit 146. In traditionaldisplay devices, a light-shielding layer is used for shielding lightleaks in such portions. However, the light-shielding layer used in atraditional display device also shields regions other than the abovecurved portion of the slit. For example, the light-shielding layer mayshield the whole region 148 including the curved portion 146B (as shownin FIG. 2C). By comparison, in the embodiments of the presentdisclosure, the extending portion 114A of the drain electrode 114 merelyshields the curved portion 146B of the slit and does not shield otherregions such as regions other than the curved portion 146B in the aboveregion 148. Therefore, the embodiments of the present disclosure mayimprove the aperture ratio of the display device.

In addition, in accordance with some embodiments of the presentdisclosure, as shown in FIG. 2C, a portion of the extending portion 114Aof the drain electrode 114 is located within the pixel aperture region144.

Next, referring to FIG. 2A, in accordance with some embodiments of thepresent disclosure, the length L of the curved portion 146B alongdirection A2 is from 2 μm to 4 μm, in which direction A2 isperpendicular to the extending direction A1 of the scan line 104.

Furthermore, in accordance with some embodiments of the presentdisclosure, the distance D1 between the end of the curved portion 146Band the first edge 116E of the gate electrode 116 along direction A2 isfrom 3 μm to 5 μm, in which direction A2 is perpendicular to theextending direction A1 of the scan line 104. The end of the curvedportion 146B is the point in the curved portion 146B which is nearest tothe gate electrode 116 or the scan line 104 along direction A2.

In other words, line 115 is the line crossing through the end of thecurved portion 146B and parallel to direction A1. The distance D1 is thedistance from line 115 to the extending line 116EA of the first edge116E along direction A2.

Moreover, the extending portion 114A includes a second edge 114AE. Thesecond edge 114AE is substantially parallel to the first edge 116E andis the edge of the extending portion 114A which is farthest from thegate electrode 116 or the scan line 104 along direction A2. In addition,at least a portion of the second edge 114AE is located within theaforementioned overlapping region.

FIG. 3A is a diagram showing the relationship between the length of theextending portion of the drain electrode within the overlapping regionand the aperture ratio in accordance some embodiments of the presentdisclosure. As shown in FIG. 3A, the horizontal axis represents theratio of [the length D2 of the extending portion 114A of the drainelectrode 114 along direction A2 within the overlapping region] and [thelength L of the curved portion 146B along direction A2]. The verticalaxis represents the aperture ratio of the pixel unit 108. It has beenshown that when the extending portion 114A of the drain electrode 114does not overlap the curved portion 146B of the slit 146 (D2/L=0), theaperture ratio of the pixel unit 108 is 50.70%. When D2/L=0.5, theaperture ratio of the pixel unit 108 is 50.05%. When the extendingportion 114A of the drain electrode 114 completely shields the curvedportion 146B of the slit 146 (D2/L=1), the aperture ratio of the pixelunit 108 is 49.41%.

Moreover, when the aperture ratio is decreased by 1%, D2/L is 0.78, andthe aperture ratio is 49.70%. The maximum value of length D2 is themaximum value of length L (4 μm) times 0.78, which is 3.12 μm. As shownin FIG. 2A, the minimum distance D3 between the first edge 116E of thegate electrode 116 and the second edge 114AE of the extending portion114A along direction A2 is the above length D2 plus distance D1.Therefore, when the aperture ratio is decreased by 1%, the maximum valueof distance D3 is the maximum value of the above length D2 (3.12 μm)plus the maximum value of distance D1 (5 μm), which is 8.12 μm or about8.2 μm.

In addition, the extending line of the second edge 114AE of theextending portion 114A is extending line 117. The length D2 describedabove is the distance between the extending line 117 and line 115 alongdirection A2. The distance D3 described above is the distance betweenthe extending line 117 and the extending line 116EA of the first edge116E along direction A2.

FIG. 3B is a diagram showing the relationship between the length of theextending portion of the drain electrode within the overlapping regionand the light transmittance in accordance with some embodiments of thepresent disclosure. As shown in FIG. 3B, the horizontal axis representsthe ratio of [the length D2 of the extending portion 114A of the drainelectrode 114 along direction A2 within the overlapping region] and [thelength L of the curved portion 146B along direction A2]. The verticalaxis represents the light transmittance of the pixel unit 108. It hasbeen shown that when the extending portion 114A of the drain electrode114 does not overlap the curved portion 146B of the slit 146 (D2/L=0),the light transmittance of the pixel unit 108 is defined as 100%. WhenD2/L=0.5, the light transmittance of the pixel unit 108 is 99.69%. Whenthe extending portion 114A of the drain electrode 114 completely shieldsthe curved portion 146B of the slit 146 (D2/L=1), the lighttransmittance of the pixel unit 108 is 98.92%.

In addition, when the light transmittance is decreased by 0.5%, D2/L is0.65, and the light transmittance is 99.50%. The maximum value of lengthD2 is the maximum value of length L (4 μm) times 0.65, which is 2.6 μm.As shown in FIG. 2A, the maximum value of distance D3 between the firstedge 116E of the gate electrode 116 and the second edge 114AE of theextending portion 114A along direction A2 is the maximum value of theabove length D2 (2.6 μm) plus the maximum value of distance D1 (5 μm),which is about 7.6 μm.

FIG. 3C is a diagram showing the relationship between the length of theextending portion of the drain electrode within the overlapping regionand the contrast ratio in accordance with some embodiments of thepresent disclosure. As shown in FIG. 3C, the horizontal axis representsthe ratio of [the length D2 of the extending portion 114A of the drainelectrode 114 along direction A2 within the overlapping region] and [thelength L of the curved portion 146B along direction A2]. The verticalaxis represents the contrast ratio of the pixel unit 108. It has beenshown that when the extending portion 114A of the drain electrode 114does not overlap the curved portion 146B of the slit 146 (D2/L=0), thecontrast ratio of the pixel unit 108 is defined as 100%. When D2/L=0.5,the contrast ratio of the pixel unit 108 is 100.96%. When the extendingportion 114A of the drain electrode 114 completely shields the curvedportion 146B of the slit 146 (D2/L=1), the contrast ratio of the pixelunit 108 is 101.49%.

In addition, when the value of D2/L is within a range from 0 to 0.2, theincrease of one unit of the D2/L value may increase the contrast ratiothe most. When D2/L=0.2, the contrast ratio is 100.45%, and the minimumvalue of length D2 is the minimum value of length L (2 μm) times 0.2,which is 0.4 μm. As shown in FIG. 2A, the minimum value of distance D3between the first edge 116E of the gate electrode 116 and the secondedge 114AE of the extending portion 114A along direction A2 is theminimum value of the above length D2 (0.4 μm) plus the minimum value ofdistance D1 (3 μm), which is about 3.4 μm.

Therefore, when the minimum distance D3 between the first edge 116E ofthe gate electrode 116 and the second edge 114AE of the extendingportion 114A along direction A2 is greater than 0 μm and is smaller than8.2 μm, the contrast ratio of the device is increased while the apertureratio and the light transmittance are merely decreased a little. Inparticular, when the minimum distance D3 between the first edge 116E ofthe gate electrode 116 and the second edge 114AE of the extendingportion 114A along direction A2 is greater than 3.4 μm and is smallerthan 7.6 μm, the contrast ratio of the device is greatly increased whilethe aperture ratio and the light transmittance are barely decreased.

Furthermore, when the area of the overlapping region between theextending portion 114A of the drain electrode 114 and the curved portion146B of the slit 146 is about 0.2 times to about 0.8 times the area ofthe curved portion 146B, such as being between about 0.3 times and about0.7 times the area of the curved portion 146B, the contrast ratio of thedevice is also greatly increased while the aperture ratio and the lighttransmittance are barely decreased.

Moreover, according to some embodiments, if the distance D3 is greaterthan 8.2 μm, or the area of the overlapping region is 0.8 times largerthan the area of the curved portion 146B, then the aperture ratio andthe light transmittance may be decreased excessively.

In accordance with some embodiments of the present disclosure, as shownin FIG. 2A, the minimum width W1 of the extending portion 114A of thedrain electrode 114 is greater than the maximum width W2 of the slit146. As a result, the extending portion 114A of the drain electrode 114may completely shield light leaks at the curved portion 146B of the slit146. Thus, the contrast ratio of the device may be increased.

It should be noted that the embodiments shown in FIGS. 1, 2A, 2B, and 2Care merely used for illustration, and the scope of the presentapplication is not intended to be limited to these particularembodiments. Except for the embodiments shown in FIGS. 1, 2A, 2B, and2C, the common electrode and the pixel electrode of the presentdisclosure may be arranged in other ways, for example, as per theembodiment shown in FIG. 4. The scope of the present disclosure is notlimited to the embodiments of FIGS. 1, 2A, 2B, and 2C.

It should be noted that the same or similar elements or layers in aboveand below contexts are represented by the same or similar referencenumerals. The materials, manufacturing methods and functions of theseelements or layers are the same or similar to those described above, andthus will not be repeated herein.

FIG. 4 is a cross-sectional view of a display device 400 in accordancewith another embodiment of the present disclosure. The differencebetween the embodiments shown in FIG. 4 and FIG. 2B is that the commonelectrode 124 is disposed on the pixel electrode 128; the commonelectrode 124 has the above-mentioned slit 146; and the pixel electrode128 is disposed between two data lines 106 in accordance with theembodiment of FIG. 4.

It should be noted that the embodiments shown in FIGS. 1, 2A, 2B, and 2Care merely used for illustration, and the scope of the presentapplication is not intended to be limited to these particularembodiments. Except for the embodiments shown in FIGS. 1, 2A, 2B, and2C, the scan lines of the present disclosure may have other patterns,for example, as in the embodiment shown in FIG. 5. The scope of thepresent disclosure is not limited to the embodiments of FIGS. 1, 2A, 2B,and 2C.

FIG. 5 is a top view of a display device 500 in accordance with anotherembodiment of the present disclosure. It should be noted that the sameor similar elements or layers in above and below contexts arerepresented by the same or similar reference numerals. The materials,manufacturing methods and functions of these elements or layers are thesame or similar to those described above, and thus will not be repeatedherein. The difference between the embodiments shown in FIG. 5 and FIG.2B is that the scan line (gate line) 150 has a curved shape in theembodiment of FIG. 5. However, the scan line (gate line) 150 alsoextends along direction A1, which is the same as the scan line (gateline) 104 in FIG. 1.

To summarize the above, in accordance with the embodiments of thepresent disclosure, the drain electrode overlaps the curved portion (orthe end portion) of the slit of the pixel electrode or the commonelectrode so as to shield light leaks of the curved portion. Moreover,in some embodiments, the aperture ratio or the contrast rate of thedisplay device is improved.

In addition, it should be noted that the drain and source mentionedabove in the present disclosure are switchable since the definition ofthe drain and source is related to the voltage connecting thereto.

Note that the above element sizes, element parameters, and elementshapes are not limitations of the present disclosure. One of ordinaryskill in the art can adjust these settings or values according todifferent requirements. It should be understood that the transistorsubstrate and the display device manufactured from the transistorsubstrate of the present disclosure are not limited to theconfigurations of FIGS. 1 to 5. The present disclosure may merelyinclude any one or more features of any one or more embodiments of FIGS.1 to 5. In other words, not all of the features shown in the figuresshould be implemented in the transistor substrate and the display devicemanufactured from the transistor substrate of the present disclosure.

Although some embodiments of the present disclosure and their advantageshave been described in detail, it should be understood that variouschanges, substitutions and alterations can be made herein withoutdeparting from the spirit and scope of the disclosure as defined by theappended claims. For example, it will be readily understood by one ofordinary skill in the art that many of the features, functions,processes, and materials described herein may be varied while remainingwithin the scope of the present disclosure. Moreover, the scope of thepresent application is not intended to be limited to the particularembodiments of the process, machine, manufacture, composition of matter,means, methods and steps described in the specification. As one ofordinary skill in the art will readily appreciate from the the presentdisclosure, processes, machines, manufacture, compositions of matter,means, methods, or steps, presently existing or later to be developed,that perform substantially the same function or achieve substantiallythe same result as the corresponding embodiments described herein may beutilized according to the present disclosure. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

What is claimed is:
 1. A transistor substrate, comprising: a pluralityof data lines; and a plurality of scan lines intersecting with theplurality of data lines to define a plurality of pixel units, whereinone of the plurality of pixel units comprises: a first electrode havinga slit, wherein the slit is substantially parallel to the plurality ofdata lines; a second electrode, wherein one of the first electrode andthe second electrode is used for receiving a pixel voltage signal, andwherein the other of the first electrode and the second electrode isused for receiving a common voltage signal; and a switching transistor,comprising: a gate electrode connecting to one of the plurality of scanlines and including a first edge substantially parallel to an extendingdirection of the plurality of scan lines; and a drain electrodeelectrically connected to one of the first electrode and the secondelectrode, and including an extending portion, wherein the extendingportion extends toward the slit and extends away from an extending lineof the first edge, and wherein the drain electrode and the slit have anoverlapping region.
 2. The transistor substrate as claimed in claim 1,wherein the extending portion comprises a second edge substantiallyparallel to the first edge, and at least a portion of the second edge islocated within the overlapping region, wherein a minimum distancebetween the first edge and the second edge is greater than 0 μm and issmaller than 8.2 μm.
 3. The transistor substrate as claimed in claim 2,wherein the minimum distance between the first edge and the second edgeis greater than 3.4 μm and is smaller than 7.6 μm.
 4. The transistorsubstrate as claimed in claim 1, wherein the slit comprises a curvedportion, and wherein the overlapping region is located within the curvedportion.
 5. The transistor substrate as claimed in claim 4, wherein theslit further comprises a major axis portion connecting to the curvedportion, and wherein an absolute value of a slope of an edge of themajor axis portion is different from a slope of an edge of the curvedportion using the extending direction of the plurality of scan lines asa basis.
 6. The transistor substrate as claimed in claim 4, wherein alength of the curved portion along a direction that is perpendicular tothe extending direction of the plurality of scan lines is from 2 μm to 4μm.
 7. The transistor substrate as claimed in claim 4, wherein adistance between an end of the curved portion and the first edge of thegate electrode along the direction that is perpendicular to theextending direction of the plurality of scan lines is from 3 μm to 5 μm.8. The transistor substrate as claimed in claim 1, wherein a minimumwidth of the extending portion of the drain electrode is greater than amaximum width of the slit.
 9. A display device, comprising a transistorsubstrate comprising: a plurality of data lines; and a plurality of scanlines intersecting with the plurality of data lines to define aplurality of pixel units, wherein one of the plurality of pixel unitscomprises: a first electrode having a slit, wherein the slit issubstantially parallel to the plurality of data lines; a secondelectrode, wherein one of the first electrode and the second electrodeis used for receiving a pixel voltage signal, and wherein the other ofthe first electrode and the second electrode is used for receiving acommon voltage signal; and a switching transistor, comprising: a gateelectrode connecting to one of the plurality of scan lines and includinga first edge substantially parallel to an extending direction of theplurality of scan lines; and a drain electrode electrically connected toone of the first electrode and the second electrode, and including anextending portion, wherein the extending portion extends toward the slitand extends away from an extending line of the first edge, and whereinthe drain electrode and the slit have an overlapping region; an opposingsubstrate disposed opposite to the transistor substrate; and a displaymedium disposed between the transistor substrate and the opposingsubstrate.
 10. The display device as claimed in claim 9, wherein theopposing substrate comprises a light-shielding layer, wherein thelight-shielding layer defines a pixel aperture region, and a portion ofthe extending portion of the drain electrode is located within the pixelaperture region.
 11. A display device, comprising a transistor substratecomprising: a plurality of data lines; and a plurality of scan linesintersecting with the plurality of data lines, wherein two adjacent scanlines and two adjacent data lines define a pixel unit, wherein the pixelunit comprises: a first electrode having a slit, wherein the slitcomprises a curved portion; a second electrode disposed corresponding tothe first electrode; and a switching transistor, comprising: a gateelectrode electrically connected to one of the plurality of scan lines,wherein the gate electrode includes a first edge substantially parallelto an extending direction of the plurality of scan lines, and the firstedge is adjacent to the slit; and a drain electrode electricallyconnected to the first electrode and one of the plurality of the datalines, wherein the drain electrode includes an extending portion, theextending portion extends away from an extending line of the first edge,and the extending portion at least partially overlaps the slit, whereinthe first electrode receives a pixel voltage signal via the drainelectrode, and the second electrode receives a common voltage signal; anopposing substrate disposed opposite to the transistor substrate; and adisplay medium disposed between the transistor substrate and theopposing substrate.